As shown in FIG. 18(A), in a conventional grid array electronic component, a via hole B of a printed wiring board K and a land L of the printed wiring board K corresponding to a large number of lands of a grid array LSI chip P mounted on the printed wiring board K are directly connected to each other through a wiring pattern H.
In a conventional wiring board having the lands (Japanese Patent Application Laid-open No.H8-213730 (improvement of a break caused by fracture based on difference of thermal expansion), Japanese Utility Model Application Laid-open Nos.S61-201374 and S62-184783 (improvement of land shape in accordance with high density of wire), Japanese Patent Publication No.S56-22151, and the like), as shown in FIG. 19, an auxiliary land AL is formed on a portion of a periphery or an entire periphery of through holes TH, and even if the through holes TH are deviated from each other, connection properties are secured.
In a conventional printed wiring board (Japanese Patent Applications Laid-open Nos.H1-115195, H11-54859 and S64-84875, as well as Japanese Patent No. 2519068), since there is a problem that if a tier drop is added to secure electrical conduction of a land in a printed board of epoxy glass or the like and to avoid a danger of brake of wire, the entire area of the land is increased and thus, density cannot be increased as compared with a case in which the tier drop is not added, a predetermined insulation gap cannot be obtained between the tier drop and another conductive circuit. Therefore, tier drops TD are offset with respect to a land L1, and the tier drops TD are formed on one side of a line or asymmetrically in a lateral direction as shown in FIG. 20.
In a mounting structure of a conventional ball grid array package (Japanese Patent Application Laid-open No.H10-335516), as shown in FIG. 21, in order to prevent thermal fatigue life of soldering from being lowered by reduction bonding force of soldering based on void caused by air trapped in the four corner via holes BH of the disposition region of a rectangular ball grid array package, flat pads PP are disposed instead of a pad BH for the via hole.
In the conventional grid array electronic component, the via hole B of the printed wiring board K and the land L of the printed wiring board K corresponding to a large number of lands of the grid array LSI chip P mounted on the printed wiring board K are directly connected to each other through the wiring pattern H. Therefore, if a load is applied to the printed wiring board K, a brake is generated in the wiring pattern H.
That is, if warpage and distortion are generated in the printed wiring board K, a great stress is applied to a connection portion between the wiring pattern H, the via hole B of the printed wiring board K and the land L of the printed wiring board K corresponding to the land of the grid array LSI chip. Therefore, a brake is generated in the connection portion of the wiring pattern H.
As shown in FIG. 19, the conventional wiring board having the land, the through holes TH are formed at a portion of its periphery or an entire periphery with an auxiliary land AL, and even if the through holes TH are offset from each other, the connection properties are obtained. Therefore, this is a technique related to a 2.54 mm pin grid array (PGA) between pins, and this is not a technique related to BGA of ball grid array LSI chip in which a large number of soldering balls having 1.27 mm pitch between pins are disposed on a lower surface of an LSI device.
In the conventional printed wiring board, if the tier drop is added to moderate the concentration of stress of the land of the printed board of epoxy glass or others of 1 mm thickness, the entire area of the land is increased. Therefore, there are problems that the density is not increased as compared with a case in which the tier drop is not added, and a predetermined insulation distance between the tier drop and other conductive circuit can not be secured. Thus, the tier drops TD are decentered with respect to the land L1, and are formed on one side of the line or asymmetrically in the lateral direction, and two leads D1 and D2 are interposed between adjacent lands L1 and L2, and this technique is judged as being one generation older technique of the ball grid array (BGA) in which a large number of surface-mounting type soldering balls of 1.27 mm pitch are disposed on a lower surface of the LSI device.
Further, in the conventional printed wiring board, since a brake of the wiring pattern when a load is applied to the printed wiring board to which the ball grid array type LSI chip is mounted is not prevented, the printed wiring board is different in wiring pattern and the like of the pitch, lead and the like of the land of the LSI device and printed board which is soldered to the printed board.
In the mounting structure of the conventional ball grid array package, a flat pad PP is disposed instead of a via hole pad BH in order to a void reduction of the soldering thermal fatigue life caused by reduction of the soldering bonding force based on void by air trapped in four corner via holes BH in disposition region of the rectangular ball grid array package, and a brake of the wiring pattern when a load is applied to the printed wiring board to which the ball grid array type LSI chip is mounted is not prevented. Therefore, the land whose wiring pattern is broken is not provided with an auxiliary land naturally.